Unless otherwise indicated herein, approaches described in this section are not prior art to the claims listed below and are not admitted to be prior art by inclusion in this section.
Processor micro-architecture and performance are strong functions of the technology used for communication among chips in a multi-chip system. The “Von Neumann bottleneck” is the path between the central processing unit (CPU) and the memory. If the bandwidth of this path is less than the CPU requirements, performance will be negatively impacted. The performance will also be negatively impacted if latency exceeds the CPU requirements. In state-of-the-art parallel processing systems, each processor chip contains multiple processing elements, or cores, has links to other processor chips, and has links to one or more memory chips.